1. Field of the Invention
The present invention generally relates to electronic data transfer devices, circuits, and methods, and more particularly to an inter-clock domain data transfer FIFO circuit for regulating the transfer of data between two clock domains of unrelated frequency.
2. Description of the Related Art
Currently, Systems-on-Chip (SoCs) are constructed using a wide range of pre-designed intellectual property modules (IPs) that are integrated together with a communication medium (typically a system bus). Each IP may have different clock and communication needs. This, coupled with the ever increasing demands on shorter time-to-market, necessitates developing efficient design flows that can achieve time closure of the whole SoC in a short time while satisfying the communication needs of its various components. Several SoC bus standards have been developed requiring either asynchronous or synchronous IP interfaces.
Due to the limitations of the aforementioned bus standards, a new, Networks-on-Chip (NoCs), interconnection paradigm has recently been proposed. NoCs are being explored as scalable interconnect architectures that can route data between SoC IPs over shared interconnects. Also, due to the difficulty of globally synchronizing SoC components, Globally Asynchronous Locally Synchronous (GALS) systems have emerged. GALS research aims at developing circuits, methodologies and models for interconnecting synchronous blocks with separate clock domains using asynchronous interconnects. Hence, NoCs can be viewed as a special case of GALS.
The data transfer rates and latencies of asynchronous interconnects are limited due to the required handshaking. It has been shown that the fastest asynchronous repeaters can, at best, only match the speed of synchronous repeaters. Loosely synchronous techniques with dedicated point-to-point connections require some form of a FIFO (First In, First Out) buffer between the transmitter and receiver to move data across their clock domains. Communication throughput and latency depends on the design of the FIFO, transmitter/receiver clock rates and communication patterns. A simple asynchronous FIFO would take at least three clock cycles of the slower of the two clocks to transfer a datum due to handshaking and synchronization between the two domains.
Several FIFO designs have been proposed to facilitate data transfer between two different clock domains. A self-timed FIFO for transferring data between two clock domains with arbitrary frequencies has been proposed. Such a FIFO would implement training circuitry to estimate the frequency difference between the two domains before data transfer can begin. From that point on, it requires that the clocks remain stable.
Synchronization is limited to what is considered as high-risk transfers. The circuit structure depends on which clock domain has the higher rate. Alternatively, a FIFO with a maximum throughput of one datum per clock cycle (of the slower of the two clocks) has been proposed. Both data and synchronization were pipelined alongside one another. This simple approach of implementing the FIFO as a pipeline greatly reduced the probability of failure due to metastability and eliminated the need for detecting full/empty conditions. However, it increased the latency of the interface, since the pipeline has to be filled first before data can come out of it. It also imposed the constraint that the sender and receiver had to operate at the same data rate.
Moreover, an approach for data transfer between different clock domains based on a general FIFO that allows the sender and receivers to put (or send) and get (or receive) data at their own clock rates simultaneously has been proposed. In addition to the need for elaborate circuitry for detecting empty/full FIFO conditions, more circuits were added to detect when the FIFO is nearly full or empty. These signals are necessary to maintain the data transfer rates while synchronizing the conventional empty/full signals. A point-to-point bidirectional link based on an asynchronous FIFO was proposed in which a datum transfer requires a minimum of three clock cycles (of the slower of the two clocks).
A FIFO-based on dual-port SRAM was proposed in which two address pointers are used to point to the beginning and end of the data in the FIFO. These pointers need to be conveyed from one clock domain to the other through synchronization. A configurable logic is used to reserve space in the FIFO to compensate for synchronization latency incurred in exchanging the address pointers between the two sides. Also, configurable delay blocks are used to control the skew of data and control signals on both sides of the FIFO, and to reserve space in the FIFO. While this implementation is well suited for large buffers, it has a complex design and significant latency.
None of the above devices taken either singly or in combination, is seen to describe the instant invention as claimed. Thus, an inter-clock domain data transfer FIFO circuit solving the aforementioned problems is desired.